Technical Field
The present disclosure relates to controlling access to a memory device.
Description of the Prior Art
It is known to provide a data processing apparatus having a memory device which has more than one storage unit in which a data item (having an associated memory address) can be stored. For example, where the memory device is a set-associative cache, a given data item can be stored in any of the multiple ways of the set-associative cache.
In this situation, it is further known for the purposes of reducing the overall access time for the memory device, to initiate a read procedure in each of the multiple storage units of the memory device before it is definitively known in which of those storage units the requested data item is stored. For example, in the context of a set-associative cache for example, it is known to perform a read procedure from all was of the cache and to rely on a tag hit (a match between the memory address of the requested data item and a stored tag portion of the memory address) to select the correct data item from each of the data items read out from the multiple ways. This technique however has the disadvantage that it comes at the price of the additional energy expenditure in performing the read out procedure from the “other” storage units (in which the requested data item is not in fact) in addition to the read out procedure performed for the storage unit in which the data item is in fact stored.
In order to seek to reduce the power consumption of a memory device having multiple storage units, it is further known to seek to predict the storage unit in which a requested data item is stored, so that only that storage unit is then accessed and additional power associated with accessing other storage units in which the data item is not stored is not expended. For example, in the context of the above mentioned set-associative cache, various “way prediction” techniques are known which determine a way in which the requested data item is stored and then only initiate the access with respect to that way. However, these techniques have the disadvantage that the way prediction then adds to the overall time taken for the retrieval of data from the memory, since additional time for the way prediction to complete can delay the start of the memory access.